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| Science & Tech /Software /Computer Assisted Design CAD /High Level Synthesis |
Behavioral Compiler from Synopsys
The vendors description of one of the best commercial tools.
(http://www.synopsys.com/products/beh_syn/beh_syn.html)
Daniel Gajski
Well known researcher.
(http://www.ics.uci.edu/~gajski/)
EDTN Links
Comprehensive list of links to information about commercial HLS tools.
(http://www.edtn.com/edatools/cae11.html)
HomeBrew
Source code for tool builders. UC Santa Barbara.
(bears.ece.ucsb.edu/homebrew/index.html)
Monet from Mentor Graphics
The vendors description of one of the best commercial tools.
(http://www.mentorg.com/monet)
NEAT
Much of the infrastructure needed to build a HLS system. Much documentation and downloadable.
(http://www.es.ele.tue.nl/neat/)
RTL/Behavioral Case Study
Overview pedagogical report
(http://server.vhdl.org/vhdl_intl/vltimes/51-CLEMENTE.html)
Visual Architect
The vendors description of one of the best commercial tools.
(http://www.cadence.com/alta/products/va_overview.html)
Open Directory - Science: Technology: Electronics: CAD
CAD CAM Solutions - Suppliers of CAD, CAM, CNC Machining and programming, mold design, high speed electrode machining and prototype model making. Center for Embedded Computer Systems - CECS is a center comprising of leading CAD, Embedded systems and Codes
(dmoz.org/Science/Technology/Electronics/CAD/)
Symbolic Techniques in High Level Synthesis
Welcome to the Home Page for High Level Synthesis at UCSB. Publications Resources BDD Boolean Calculator HomeBrew Personnel Statistics Frequently Accessed Documents Miscellaneous VLSI Testing, ...
(bears.ece.ucsb.edu/Home.html)
Untitled
AREAS OF RESEARCH ARCHITECTURAL SYNTHESIS OF COMPUTER SYSTEMS high-level synthesis testability issues in high-level synthesis PARALLEL COMPUTATION resource optimization in parallel computer systems mapping of algorithms onto parallel computer architecture
(http://martin.ijs.si/fle7areas.html)
Personal Data for Juan Carlos López
Associate Professor ETSI Telecomunicación Ciudad Universitaria s/n E-28040 Madrid Spain - (Europe) CAD Tools for Electronic Systems Design Specification of Electronic Systems
(http://www-lsi.die.upm.es/~lopez/index.html)
Jui-Ming Chang
General research interests: various levels of the VLSI CAD (from physical design to system level) Ph.D. Dissertation: Formal Methods for Behavioral and System Level Power Optimization and Synthesis
(atrak.usc.edu/~juiming/)
kurdahi research
This page is permanently under construction I have been working in the area of VLSI CAD since 1983. Specifically, my research interests are in high-level synthesis, estimation, and design methodology of large scale (mostly digital) systems.
(http://www.eng.uci.edu/faculty/kurdahi/mybio.html)
Selected SIGDA Conference Tutorials
Design Automation Conference 95 Parallel Logic Simulation of VLSI Systems. Roger D. Chamberlain. Productivity Issues in High-Level Design: Are Tools Solving the Real Problems?
(http://www.c-lab.de/~wolfgang/wm.tutorial.html)
Computer-Aided Design
The work in computer-aided design is divided into two groups. The high-level synthesis group is investigating issues in mapping behavioral specifications to register transfer level representations.
(http://www-cse.ucsd.edu/Research/cad.html)
FPGA
We are working on both CAD for FPGA design and straight FPGA design, trying to find good architectures for solving diffcult problems using FPGAs as a rapid prototyping environment.
(http://www.cse.cuhk.edu.hk/~phwl/fpga.html)
UCSB CAD and Test Group
Class Links Analog/mixed-signal testing Delay testing Use of emulation engine for fault grading ATPG-based logic optimization Sequential circuit equivalence verification
(bears.ucsb.edu/)
1992 High Level Synthesis Benchmarks
No Description available
(cbl.ncsu.edu/CBL_Docs/hls92.html)
High Level Synthesis Resources
No Description available
(bears.ece.ucsb.edu/cad/)
1989 High Level Synthesis Benchmarks
No Description available
(http://zodiac.cbl.ncsu.edu/CBL_Docs/hls89.html)
High-Level Synthesis of Digital Systems
No Description available
(http://www.ida.liu.se/~cadlab/synthesis.html)
Symbolic Techniques in High Level Synthesis
No Description available
(bears.ucsb.edu/Home.html)
The High Level Synthesis Page
No Description available
(dynamo.ecn.purdue.edu/~vlsi/technology.html)
Parallel Algorithms For High-Level Synthesis
No Description available
(http://www.ece.uc.edu/~ddel/theses/jroy.html)
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